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TDA9106A
LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PRELIMINARY DATA
GENERAL SYNC PROCESSOR HOR. & VERT. SYNC OUTPUT FOR MCU HOR. & VERT. BLANKING OUTPUTS 12V SUPPLY VOLTAGE 8V REFERENCE VOLTAGE HOR. & VERT. LOCK UNLOCK OUTPUTS READ/WRITE I 2C INTERFACE HORIZONTAL MOIRE OR DAC OUTPUT
. . . . . . . . . . . . . . . . . . . .
HORIZONTAL SELF-ADAPTATIVE DUAL PLL CONCEPT 150kHz MAXIMUM FREQUENCY X-RAY PROTECTION INPUT I2C CONTROLS : HORIZONTAL POSITION, FREQUENCY GENERATOR FOR BURN-IN MODE VERTICAL VERTICAL RAMP GENERATOR 50 TO 165Hz AGC LOOP GEOMETRY TRACKING WITH V-POS & AMP I2C CONTROLS : V-AMP, V-POS, S-CORR, C-CORR I2C GEOMETRY CORRECTIONS VERTICAL PARABOLA GENERATOR (Pincushion, Keystone, Corner Correction, Top/bottom Corner Correction Balance) HORIZONTAL DYNAMIC PHASE (Side Pin Balance & Parallelogram) HORIZONTAL AND VERTICAL DYNAMIC FOCUS (Horizontal Focus Amplitude, Horizontal Focus Symmetry)
Combined with ST7275 Microcontroller family, TDA9206 (Video preamplifier) and STV942x (On-Screen Display controller) the TDA9106A allows to built fully I2 C bus controlled computer display monitors, thus reducing the number of external components to a minimum value.
SHRINK42 (Plastic Package) ORDER CODE : TDA9106A
PIN CONNECTIONS
S/G MOIRE PLL1INHIB PLL2C HREF HFLY HGND FC2 FC1 C0 R0 PLL1F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 GND SDA SCL 5V H/HVIN HLOCKOUT HOUT VSYNCOUT TEST VSYNCIN VFOCUS EWOUT VFLY VOUT VDCOUT VCAP VREF VAGCCAP VGND VBLKOUT HBLKOUT
9106A-01.EPS
DESCRIPTION The TDA9106A is a monolithic integrated circuit assembled in 42 pins shrunk dual in line plastic package.This IC controlsall the functionsrelated to the horizontal and vertical deflection in multimodes or multi-frequency computer display monitors. The internal sync processor, combinedwith thevery powerful geometry correction block are making the TDA9106Asuitablefor very high performancemonitors with very few external components. It is particularly well suited for high-end 15" and 17" monitors.
November 1997
HLOCKCAP HPOS XRAY HFOCUSCAP HFOCUS V CC GND HOUTEM HOUTCOL
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This is advance information on a new product now in development or undergoing evaluatio n. Details are subject to change without notice.
TDA9106A
PIN CONNECTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Name S/G MOIRE PLL1 INHIB PLL2C HREF HFLY HGND FC2 FC1 C0 R0 PLL1F HLOCKCAP HPOS XRAY HFOCUSCAP HFOCUS VCC GND HOUTEM HOUTCOL HBLKOUT VBLKOUT VGND VAGCCAP VREF VCAP VDCOUT VOUT VFLY EWOUT VFOCUS VSYNCIN TEST VSYNCOUT HOUT HLOCKOUT H/HVIN 5V SCL SDA GND Sync on green input Moire output TTL-Compatible input for PLL1 inhibition Second PLL Loop Filter Horizontal Section Reference Voltage (to filter) Horizontal Flyback Input (positive polarity) Horizontal Section Ground VCO Low Threshold filtering Capacitor VCO High Threshold filtering Capacitor Horizontal Oscillator Capacitor Horizontal Oscillator Resistor First PLL Loop Filter First PLL Lock/Unlock Time Constant Capacitor Horizontal Centering Output (to filter) X-RAY protection input (with internal latch function) Horizontal Dynamic Focus Oscillator Capacitor Horizontal Dynamic Focus Output Supply Voltage (12V Typ) General Ground (related to VCC) Horizontal Drive Output (internal transistor emitter) Horizontal Drive Output (int. trans. open collector) Horizontal Blanking Output (see activation table) Vertical Blanking Output (see activation table) Vertical Section Ground Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator Vertical Section Reference Voltage (to filter) Vertical Sawtooth Generator Capacitor Vertical Position Reference Voltage Output Vertical Ramp Output (with frequency independant amplitude and S or C Corrections if any) Vertical Flyback Input (positive polarity) East/West Pincushion Correction Parabola Output (with Corner corrections if any) Vertical Dynamic Focus Output TTL-compatible Vertical Sync Input (for separated H&V) Not to be used - Test pin TTL Vertical Sync Output (Extracted VSYNC in case of S/G or TTL Composite HV Inputs) TTL Horizontal Sync Output (To be used for frequency measurement) First PLL Lock/Unlock Output (5V unlocked - 0V locked) TTL-compatible Horizontal Sync Input Supply Voltage (5V Typ.) I C-Data input Ground (Related to 5V)
2
9106A-01.TBL
Function
I2C-Clock input
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TDA9106A
QUICK REFERENCE DATA
Parameter Horizontal Frequency Autosynch Frequency (for given R0 and C0) Horizontal Sync Polarity Input Polarity Detection (on both Horizontal and Vertical Sections) TTL Composite Synch or Sync on Green Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section) I C Control for H-Position XRay Protection Fixed Horizontal Duty Cycle I C Free Running Adjustment Stand-by Function Two Polarities H-Drive Outputs Supply Voltage Monitoring PLL1 Inhibition Possibility Blanking Outputs (both Horizontal and Vertical) Vertical Frequency Vertical Autosync (for 150nF) Vertical S-Correction Vertical C-Correction Vertical Amplitude Adjustment Vertical Position Adjustment East/West Parabola Output Pin Cushion Correction Amplitude Adjustment Keystone Adjustment Corner and Corner Balance Adjustments Internal Dynamic Horizontal Phase Control Side Pin Balance Amplitude Adjustment Parallelogram Adjustment Tracking of Geometric Corrections Reference Voltage (both on Horizontal and Vertical) Dynamic Focus (both Horizontal and Vertical) I C Horizontal Dynamic Focus Amplitude Adjustment I C Horizontal Dynamic Focus Keystone Adjustment Type of Input Sync Detection (supplied by 5V Digital Supply) Horizontal Moire Output I2C Controlled H-Moire Amplitude Frequency Generator for Burn-in Fast I2C Read/Write
2 2 2 2
Value 15 to 150 1 to 4.5 YES YES YES YES 10 YES 48 NO YES YES YES YES YES 35 to 200 50 to 165 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES 400 YES
Unit kHz FH
% % F0
Hz Hz
kHz
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9106A-02.TBL
PLL1INHIB
PLL1F
HPOSFILTER
HLOCKOUT HLOCKCAP
R0
C0
FC1
FC2
HFLY
PLL2C
HOUTCOL HOUTEM
VFLY
VSYNC
HFLY
LOCK
VCAP
VAGCCAP
VDCOUT
VOUT
9106A-02.EPS
VFOCUS
4/30
12 14 37 13 11 10 9 8 6 4 21 20
TDA9106A
BLOCK DIAGRAM
3
GND 19 PHASE/FREQUENCY COMPARATOR H-PHASE (7 bits) VCO PHASE COMPARATOR PHASE SHIFTER HOUT BUFFER
HREF
5
VREF
HGND Safe Freq. 2 bits H-SAWTOOTH GENERATOR LOCK/UNLOCK IDENTIFICATION Spin Bal 6 bits X2 Key Bal 6 bits SYNC INPUT SELECT (2 bits) SYNC PROCESSOR X Amp & Keyst 2 x 5 bits
7
SAFETY PROCESSOR
18 VCC 15 X-RAY 16
VFLY 30
HFOCUS CAP X2
17 HFOCUS
HBLKOUT 22
BLANKING GENERATOR
VBLKOUT 23
VSYNCOUT 35
HOUT 36
MOIRE PROCESSOR 5 BITS
2
MOIRE
S/G
1
H/HVIN 38
H-FLY
VSYNC
VSYNCIN 33 GEOMETRY TRACKING 6 bits 6 bits VPOS 7 bits CORNER CORRECTION (2 x 6 bits) 6 bits X2
31 EWOUT
VREF 26
VREF
VGND 24
TEST 34
5V 39 S AND C CORRECTION
RESET GENERATOR VERTICAL OSCILLATOR RAMP GENERATOR VAMP 7 bits
27 25 28 29 32
SDA 41
X2
7 bits X
SCL 40
I2C INTERFACE
GND 42
TDA9106
TDA9106A
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VDD VIN Supply Voltage (Pin 18) Supply Voltage (Pin 39) Max Voltage on Pin 6 Pins 15, 21, 22, 23 Pin 1 Pin 4 Pins 3, 33,34,37,38,40,41 Pin 16 Pins 8, 9, 10, 11, 12, 13, 14, 25, 27, 30 ESD susceptibility Human Body Model,100pF Discharge through 1.5k EIAJ Norm,200pF Discharge through 0 Storage Temperature Junction Temperature Operating Temperature Parameter Value 13.5 5.7 1.8 12 3.6 4 5 6 8 2 300 -40, +150 +150 0, +70 Unit V V V V V V V V V kV V
o o o
VESD
Tj Toper
C C
THERMAL DATA
Symbol Rth (j-a) Parameter Junction-ambient Thermal Resistance Max. Value 65 Unit
o
C/W
SYNCHRO PROCESSOR Operating Conditions
Symbol HsVR MinD Mduty VsVR VSW VSmD VextM Parameter Horizontal Sync Input Voltage Minimum Horizontal Input Pulses Duration Maximum Horizontal Input Signal Duty Cycle Vertical Sync Input Voltage Minimum Vertical Sync Pulse Width Maximum Vertical Sync Input Duty Cycle M ax i m um V er t ic al Syn c W i dt h on T T L H/Vcomposite or S/G Test Conditions Pin 38 Pin 38 Pin 38 Pin 33 Pin 33 Pin 33 Pins 1, 38 0 5 15 750 Min. 0 0.7 25 5 Typ. Max. 5 Unit V s % V s % s
Electrical Characteristics (VDD = 5V, Tamb = 25oC)
Symbol VSGDC ISGbias VSGTh VINTH RIN VOut TfrOut VHlock VoutT Parameter S/G Clamped DC Level Internal Diode Bias Current Slicing Level (see application design choice) H o r iz on t al a n d V ert i cal I npu t V o lta ge (Pins 33,38) Horizontal and Vertical Pull-Up Resistor Output Voltage (Pins 35,36,37) Falling and Rising Output CMOS Buffer Horizontal 1st PLL Lock Output Status (Pin 37) Extracted Vsync Integration Time (% of TH) on H/V Composite or S/G Test Conditions Pin 1, I1 = -1A Pin 1, V1 = 1.6V Pin 1 Low Level High Level Pins 33,38 Low level High Level Pins 35,36,37 Cout = 20pF Locked Unlocked Pin 35, C0 = 820pF 26 2.2 200 0 5 100 0 5 35 Min. Typ. 1 10 0.2 0.8 Max. Unit V A V V V k V V ns V V %
5/30
9106A-05.TBL
9106A-04.TBL
9106A-03.TBL
Tstg
C
TDA9106A
I2C READ/WRITE Electrical Characteristics (VDD = 5V,Tamb = 25oC)
Symbol I2C PROCESSOR Fscl Tlow Thigh Vinth VACK Maximum Clock Frequency Low period of the SCL Clock High period of the SCL Clock SDA and SCL Input Threshold Acknowledge Output Voltage on SDA input with 3mA Pin 40 Pin 40 Pin 40 Pins 40,41 Pin 41 400 1.3 0.6 2.2 0.4 kHz s s V V Parameter Test Conditions Min. Typ. Max. Unit
See also I2C Table Control and I2C Sub Address Control
HORIZONTAL SECTION Operating Conditions
Symbol VCO R0(Min.) C0(Min.) F(Max.) Minimum Oscillator Resistor Minimum Oscillator Capacitor Maximum Oscillator Frequency Pin 11 Pin 10 6 390 150 k pF kHz Parameter Test Conditions Min. Typ. Max. Unit
OUTPUT SECTION I6m HOI1 HOI2 Maximum Input Peak Current Horizontal Drive Output Maximum Current Pin 20 Pin 21 Pin 6 Sourced current Sunk current 2 20 20 mA mA mA
Electrical Characteristics (VCC = 12V, Tamb = 25oC)
Symbol Parameter Test Conditions Min. Typ. Max. Unit SUPPLY AND REFERENCE VOLTAGES VCC VDD ICC IDD VREF-H VREF-V IREF-H IREF-V Supply Voltage Supply Voltage Supply Current Supply Current Horizontal Reference Voltage Vertical Reference Voltage Max. Sourced Current on VREF-H Max. Sourced Current on VREF-V Pin 18 Pin 39 Pin 18 Pin 39 Pin 5, I = 5mA Pin 5, I = 5mA Pin 5 Pin 26 7.4 7.4 10.8 4.5 12 5 50 5 8 8 8.6 8.6 5 5 13.2 5.5 V V mA mA V mA mA
9106A-05.TBL
V
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TDA9106A
HORIZONTAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued)
Symbol 1st PLL SECTION HpolT VVCO Polarity Integration Delay VCO Control Voltage (Pin12) VREF-H = 8V f0 fH(Max.) R0 = 6.49k, C0 = 820pF, dF/dV = 1/11R0C0 % of Horizontal Period Sub-Address 01, Pin 14 Byte x1111111 Byte x1000000 Byte x0000000 R0 = 6.49k, C0 = 820pF, f0 = 0.97/8R0C 0 0.75 VREF-H / 6 6.2 17 10 2.8 3.4 4.0 22.3 -150 R0 = 6.49k, C0 = 820pF, from f0+0.5kHz to 4.5F0 fH(Min.) fH(Max.) Typ Threshold = 1.6V PLL ON PLL OFF Sub-Address 02 2F0 3F0 Pin 9 To filter Pin 8 To filter 6.4 1.6 V V ms V V kHz/V % V V V kHz ppm/C Parameter Test Conditions Min. Typ. Max. Unit
Vcog Hph Hphmin Hphtyp Hphmax f0 dF0/dT CR
VCO Gain (Pin 12) Horizontal Phase Adjustment Horizontal Phase Decoupling Output Minimum Value Typical Value Maximum Value Free Running Frequency Free Running Frequency Thermal Drift (No drift on external components) PLL1 Capture Range
23.5 100 0.8 2
kHz kHz V V
PLLinh
PLL1 Inhibition (Pin3)
SFF
Safe Forced Frequency SF1 Byte 11xxxxxx SF2 Byte 10xxxxxx VCO Sawtooth Level High FC1=(4.VREF-H)/5 Low FC2=(VREF-H)/5
FC1 FC2
2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION FBth Hjit Flyback Input Threshold Voltage (Pin 6) Horizontal Jitter (see Pins 8-9 filtering) Horizontal Drive Output Duty-Cycle (Pin 20 or 21) (see Note 1) XRAYth Vphi2 VSCinh IHblk VHblk X-RAY Protection Input Threshold Voltage Internal Clamping Levels on 2nd PLL Loop Filter (Pin 4) Threshold Voltage To Stop H-Out,V-Out when V CC < VSCinh Maximum Horizontal Blanking Output Current Horizontal Blanking Output Low Level (Blanking ON) Horizontal Drive Output Low Level (Pin 20 to GND) High Level (Pin 21 to VCC=12V) Pin 15 Low Level High Level Pin 18 I22 V22 with I22 = 10mA 0.25 0.65 0.75 TBD 48 8 1.6 4.0 7.5 10 0.5 V ppm % V V V V mA V
9106A-05.TBL
HDvd HDem
V21-V20, IOUT = 20mA V20, IOUT = 20mA
9.5
1.1 10
1.7
V V
Notes : 1. Duty Cycle is the ratio of power transistor OFF time to period. Power transistor is OFF when output transistor is OFF. 2. Initial Condition for Safe Operation Start Up (Max. duty cycle).
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TDA9106A
HORIZONTAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit HORIZONTAL DYNAMIC FOCUS SECTION HDFst Horizontal Dynamic Focus Sawtooth Minimum Level Maximum Level Horizontal Dynamic Focus Sawtooth Discharge Width Bottom DC Output Level DC Output Voltage Thermal Drift Horizontal Dynamic Focus Amplitude Min Byte xxx11111 Typ Byte xxx10000 Max Byte xxx00000 Horizontal Dynamic Focus Keystone Min A/B Byte xxx11111 Typ Byte xxx10000 Max A/B Byte xxx00000 MOIRE OUTPUT RMOIRE VMOIRE Minimum Output Resistor Output Voltage (moire off), Subaddress 0F Pin 2 Pin 2, RMOIRE = 2k Byte 0xx00000 Byte 0xx10000 Byte 0xx11111 2 0.2 1.1 2.0 k V V V
9106A-05.TBL
HfocusCap = C0 = 820pF, fH = 90kHz, Pin 16 Driven by Hfly RLOAD = 10k, Pin 17 Sub-Address 03, Pin 17, fH = 90kHz, Keystone Typ
2 4.7 500 2 200 1 1.5 3
V V ns V ppm/C VPP VPP VPP
HDFdis HDFDC TDHDF HDFamp
HDFKeyst
Sub-Address 04, fH = 90kHz, Typ Amp B/A A/B A/B
3.5 1.0 3.5
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TDA9106A
VERTICAL SECTION Operating Conditions
Symbol OUTPUTS SECTION VEWM VEWm VDFm R LOAD Maximum EW Output Voltage Minimum EW Output Voltage Minimum Vertical Dynamic Focus Output Voltage Minimum Load for less than 1% Vertical Amplitude Drift Pin 31 Pin 31 Pin 32 Pin 25 1.8 1.8 65 6.5 V V V M Parameter Test Conditions Min. Typ. Max. Unit
Electrical Characteristics (VCC = 12V, Tamb = 25oC)
Symbol VERTICAL RAMP SECTION VRB VRT VRTF VSTD VFRF ASFR RAFD Rlin Vpos Voltage at Ramp Bottom Point Voltage at Ramp Top Point (with Sync) VREF-V Voltage at Ramp Top Point (without Sync) Vertical Sawtooth Discharge Time Duration (Pin 27) Vertical Free Running Frequency (see Notes 3 & 4) AUTO-SYNC Frequency Ramp Amplitude Drift Versus Frequency at Maximum Vertical Amplitude Ramp Linearity on Pin 27 (see Notes 3 & 4) Vertical Position Adjustment Voltage (Pin28) VREF-V=8V, Pin 27 Pin 27 Pin 27 With 150nF Cap COSC (Pin 27) = 150nF Measured on Pin27, C27 = 150nF 5% See Note 5 C27 = 150nF 50Hz < f and f < 165Hz 2.5 < V27 and V27 < 4.5V Sub Address 06 Byte x0000000 Byte x1000000 Byte x1111111 Pin 28 Sub Address 05 Byte x0000000 Byte x1000000 Byte x1111111 See Note 6, Pin 29 Subaddress 07 V/VPP at T/4 V/VPP at 3T/4 SubAddress 08 Byte x1000000 Byte x1100000 Byte x1111111 Pin 30 See Note 7, Pin 30 7.5 50 200 0.5 3.2 3.5 3.8 2 2.25 3 3.75 3.5 5 -4 +4 -3 0 3 1 2.5 3.3 2 5 VRT0.1 80 100 165 TBD V V V s Hz Hz ppm/Hz % V V V mA V V V V mA % % % % % V V Parameter Test Conditions Min. Typ. Max. Unit
3.65
IVPOS VOR
Max Current on Vertical Position Output Vertical Output Voltage (peak-to-peak on Pin 29)
3.5
VoutDC VOI dVS
DC Voltage on Vertical Output Vertical Output Maximum Current (Pin29) Max Vertical S-Correction Amplitude x0xxxxxx inhibits S-CORR x1111111 gives max S-CORR Vertical C-Corr Amplitude x0xxxxxx inhibits C-CORR
Ccorr
VflyTh VflyInh
Vertical Flyback Threshold Inhibition of Vertical Flyback Input
Notes : 3. With Register 07 at Byte x0xxxxxx (Vertical S-Correction Control) then the S correction is inhibited, consequently the sawtooth has a linear shape. 4. With Register 08 at Byte x0xxxxxx (Vertical C - Correction Control) then the C correction is inhibited, consequently the sawtooth has a linear shape. 5. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value on Pin 27 and with a constant ramp amplitude. 6. VOUTDC = (7/16).VREF-V. Typically 3.5V for Vertical reference voltage typical value (8V). 7. When Pin 30 ( VREF-V) - 0.5V, Vfly input is inhibited and vertical blanking on vertical blanking output is replaced by vertical sawtooth discharge time.
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9106A-05.TBL
TDA9106A
VERTICAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued)
Symbol EAST/WEST FUNCTION EWDC TDEWDC EWpara DC Output Voltage with Typ Vpos,Keystone, Corner and Corner Balance Inhibited DC Output Voltage Thermal Drift Parabola Amplitude with Vamp Max, V-Pos Typ, Keystone, Corner and Corner Balance Inhibited Pin 31, see Figure 1 See Note 8 Subaddress 09 Byte 1x111111 Byte 1x100000 Byte 1x000000 Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 0A Byte 10000000 Byte 11111111 Subaddress 06 2.5 100 2.6 1.4 0 0.45 0.8 1.4 V ppm/C V V V V V V Parameter Test Conditions Min. Typ. Max. Unit
EWtrack
Parabola Amplitude Function of V-AMP Control (tracking between V-AMP and E/W) with Typ Vpos, Keystone, Corner and Corner Balance Inhibited, EW Typ Amplitude (see Note 9) Keystone Adjustment Capability with Typ Vpos, Corner and Corner Balance Inhibited, EW Inhibited and Vertical Amplitude Max (see Note 9 and Figure 4) Intrinsic Keystone Function of V-POS Control (tracking between V-POS and EW) with Corner and Corner Balance Inhibited, EW Max Amplitude and Vertical Amplitude Max (see Note 9) A/B Ratio B/A Ratio Max Corner Correction Amplitude with Vamp Max, V-POS Typ, EWamp, Keystone and Corner Balance Inhibited (see Note 9) Max Corner Balance Correction Amplitude with Vamp Max, V-POS Typ, EWamp, Keystone and Corner Inhibited Subaddress 0C (see Note 9)
KeyAdj
1 1
VPP VPP
KeyTrack
Byte x0000000 Byte x1111111 Subaddress 0B EWout at T/6, 5T/6 Byte x1111111 Byte x1000000 Byte 01111111 EWout at T/4 EWout at 3T/4 Byte 01000000 EWout at T/4 EWout at 3T/4
0.5 0.5
Corner Max
+0.2 -0.2 +0.2 -0.2 -0.2 +0.2
V V V V V V
Corner BalMax
INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION SPBpara Side Pin Balance Parabola Amplitude (Figure 2) with Vamp Max, V-POS Typ and Parallelogram Inhibited (see Notes 9 & 10) Side Pin Balance Parabola Amplitude function of Vamp Control (tracking between Vamp and SPB) with SPB Max, V-POS Typ and Parallelogram Inhibited (see Notes 9 & 10) Parallelogram Adjustment Capability with Vamp Max, V-POS Typ and SPB Inhibited (see Notes 9, 10 & 11) Intrinsic Parallelogram Function of Vpos Control (tracking between V-Pos and DHPC) with Vamp Max, SPB Max and Parallelogram Inhibited (see Notes 9 & 10) A/B Ratio B/A Ratio Subaddress 0D Byte x1111111 Byte x1000000 Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 0E Byte x1111111 Byte x1000000 Subaddress 06 1.4 -1.4 0.5 0.9 1.4 1.4 -1.4 %TH %TH %TH %TH %TH %TH %TH
SPBtrack
ParAdj
Partrack
Byte x0000000 Byte x1111111
0.5 0.5
Notes : 8. These parameters are not tested on each unit. They are measured during our internal qualification 9. Refers to Notes 3 & 4 from last section. 10.TH is the Horizontal PLL Period Duration. 11.Figure 2 is representing effect of dynamic horizontal phase control.
10/30
9106A-05.TBL
TDA9106A
VERTICAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit VERTICAL DYNAMIC FOCUS FUNCTION VDFDC TDVDFDC VDFAMP DC Output Voltage with V-Pos Typ DC Output Voltage Thermal Drift Parabola Amplitude Function of Vamp (tracking between Vamp and VDF) with V-Pos Typ (see Figure 3) (see Note 13) Parabola Assymetry Function of VPos Control (tracking between V-Pos and VDF) with Vamp Max. (see Note 13) See Figure 3 See Note 12 Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 06 Byte x0000000 Byte x1111111 6 100 0.9 1.6 2.5 0.5 0.5 V ppm/C V V V
9106A-05.TBL
VDFKEY
Notes : 12. Parameter not tested on each unit but measured during our internal qualification procedure including batches coming from corners of our process and also temperature characterization. 13. S and C corrections are inhibited so the output sawtooth has a linear shape.
Figure 1 : E/W Output
Figure 2 :
Dynamic Horizontal Phase Control Output
B A EWPARA
A
B
9106A-03.EPS
EWDC
SPBPARA
DHPCDC
Figure 3 : Vertical Dynamic Focus Function
Figure 4 :
Keystone Effect on E/W Output (PCC Inhibited)
A VDFDC VDFAMP B
9106A-05.EPS
Keyadj
9106-06A.EPS
11/30
9106A-04.EPS
TDA9106A
TYPICAL VERTICAL OUTPUT WAVEFORMS
Function Sub Address Pin Byte Specification Picture Image
2.25V
10000000 Vertical Size 05 29 11111111
3.75V
Vertical Position DC Control
06
28
x0000000 x1000000 x1111111
3.2V 3.5V 3.8V
x0xxxxxx Inhibited Vertical S Linearity 07 29 x1111111
VPP V = 4% V PP
9106A-06.TBL / 9106A-07.EPS TO 9106A-13.EPS
V
x1000000 Vertical C Linearity 08 29
VPP
V V = 3% V PP V
x1111111
VPP V = 3% V PP
12/30
TDA9106A
GEOMETRY OUTPUT WAVEFORMS
Function Sub Address Pin Byte EWamp Typ. 10000000 Trapezoid Control 0A 31 11111111
2.5V 3.75V 2.75V
Specification
3.75V 2.75V
Picture Image
2.5V
Keystone Inhibited Pin Cushion Control 1x000000 09 31
2.5V 2.5V 0V
1x111111
SPB Inhibited Parrallelogram Control x1000000 0E Internal x1111111
3.7V 1.4% TH 3.7V 1.4% TH
3.7V 1.4% TH
Side Pin Balance Control
X10000000 0D Internal x1111111
1.4% TH 3.7V
Vertical Dynamic Focus
6V
32
2.5V
13/30
9106A-07.TBL / 9106A-14.EPS TO 9106A-22.EPS
Parallelogram Inhibited
TDA9106A
GEOMETRY OUTPUT WAVEFORMS (continued)
Function Sub Address Pin Byte EWamp Typ. x1111111 Specification
Corner effect
Picture Image
without Corner
Corner Control
0B
31
01000000
Corner effect
EWamp Typ. 10000000
Corner effect
9106A-07.TBL / 9106A-23.EPS TO 9106A-30.EPS
Corner Balance Control
0C
31 Corner effect 11111111
Note : The specification of output voltage is indicated on 3.75VPP vertical sawtooth output condition.The output voltage depends on vertical sawtooth output voltage.
14/30
TDA9106A
I2C BUS ADDRESS TABLE Sub Address Definition Slave Address (8C) : Write Mode
D8 0 1 2 3 4 5 6 7 8 9 A B C D E F x x x x x x x x x x x x x x x x D7 x x x x x x x x x x x x x x x x D6 x x x x x x x x x x x x x x x x D5 x x x x x x x x x x x x x x x x D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Horizontal Drive Selection Horizontal Position Safety Frequency Synchro Priority / Horizontal Focus Amplitude Refresh / Horizontal Focus Keystone Vertical Ramp Amplitude Vertical Position Adjustment S Correction C Correction E/W Amplitude E/W Keystone Cbow Corner Spin Corner Side Pin Balance Parallelogram Moire Control Amplitude
Slave Address (8D) : Read Mode
D8 0 x D7 x D6 x D5 x D4 0 D3 0 D2 0 D1 0 Synchro and Polarity Detection
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TDA9106A
I2C BUS ADDRESS TABLE (continued) Table : Register Map
D8 WRITE MODE 00 Blk Sel 1, Blk [0] Xray 1, reset [0] HDrive 0, off [1], on Horizontal Phase Adjustment [1] [0] [0] [0] [0] [0] [0] D7 D6 D5 D4 D3 D2 D1
01
02
Safety Frequency 1, on 1, F0 x 2 [0], off [0], F0 x 3 Sync Priority 0, Vextr 0, S/G [1], Vin [1], H/V Detect Refresh [0], off Vramp 0, off [1], on Horizontal Focus Amplitude [1] [0] [0] [0] [0]
03
Horizontal Focus Keystone [1] [0] [0] [0] [0]
04
Vertical Ramp Amplitude Adjustment [1] [1] S Select 1, on [0] C Select 1, on [0] [0] [0] [1] [0] [0] [0] [0] [0] [0] [0] [0] [0]
05 06 07
Vertical Position Adjustment [0] [0] [0] S Correction [0] [0] [0]
C Correction [1] [0] [0] [0] [0] [0]
08 EW Sel 0, off [1] EW Key 0, off [1] Test H 1, on [0], off Test V 1, on [0], off
East/West Amplitude [1] [0] [0] East/West Keystone [1] Cbow Sel 1, on [0] Spin Sel 1, on [0] SPB Sel 0, off [1] Parallelo 0, off [1] [0] [0] [0] [0] [0] [0] [0] [0] [0]
09
0A
Cbow Corner [1] [0] [0] [0] [0] [0]
0B
Spin Corner [1] [0] [0] [0] [0] [0]
0C
Side Pin Balance [1] [0] [0] [0] [0] [0]
0D
Parallelogram [1] [0] [0] [0] Moire Control [0] [0] [0] [0] [0] [0] [0]
0E Moire 1, on [0], off
0F
READ MODE 00 Hlock 0, on [1], no Vlock 0, on [1], no Xray 1, on [0], off Polarity Detection H/V pol V pol [1], negative [1], negative Vext det [0], no det Synchro Detection H det V det [0], no det [0], no det
[ ] initial value
16/30
TDA9106A
OPERATING DESCRIPTION I - GENERAL CONSIDERATIONS I.1 - Power Supply The typical values of the power supply voltages VCC and VDD are respectively 12V and 5V. Perfect operationis obtained if VCC and VDD are maintened in the limits : 10.8 to 13.2V and 4.5 to 5.5V. In order to avoid erratic operation of the circuit during transient phase of VCC switching on, or switching off, the value of VCC is monitored and the outputsof the circuit are inhibited if VCC is less than 7.5V typically. In the same manner,VDD is monitored and internal set-up is made until VDD reaches 4V (see I2C Control Table for power on reset). In order to have a verygood powersupply rejection, the circuit is internally powered by several internal voltage references (the unique typical value of which is 8V). Two of these voltage references are externally accessible, one for the vertical part and one for the horizontal one. If needed,these voltage references can be used (until load is less than 5mA).Furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor connectedto ground,in order to minimize the noise and consequently the "jitter" on vertical and horizontal output signals. I.2 - I2C Control TDA9106A belongs to the I2C controlled device family, instead of being controlled by DC voltages on dedicated control pins, each adjustment can be realized through the I2C Interface. The I2C bus is a serial bus with a clock and a data input. Thegeneral functionand thebus protocolare specified in the Philips-bus data sheets. The interface (Data and Clock) is TTL-level compatible. The internal threshold level of the input comparator is 2.2V (when VDD is 5V). Spikes of up to 50ns are filtered by an integrator and maximum clock speed is limited to 400kHz. The data line (SDA) can be used in a bidirectional way that means in read-mode the IC clocks out a reply information (1 byte) to the micro-processor. The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to transmit the IC-address(7 bits-8C) and the read/write bit (0 write - 1 read). I.3 - Write Mode In write mode the second byte sent contains the subaddress of the selected function to adjust (or controlsto affect)and the thirdbyte the corresponding data byte.It is possible to send more than one data byte to the IC. If after the third byte no stop or start condition is detected, the circuit increments automatically the momentary subaddress in the subaddress counter by one (auto-increment mode). So it is possible to transmit immediately the next data bytes without sending the IC address or subaddress.It can be useful so as to reinitialize the whole controls very quickly (flash manner). This procedure can be finished by a stop condition. The circuit has 14 adjustment capabilities : 1 for Horizontal part, 4 for Vertical one, 2 for E/W correction, 2 for original Corner correction, 2 for the Dynamic Horizontal phase control,1 for Moire option and 2 for Horizontal Dynamic Focus. 20 bits are also dedicated to several controls (ON/OFF, Horizontal Safety Frequency, Synchro Priority, Detection Refresh and Xray reset). I.4 - Read Mode During read mode the second byte transmits the reply information. The reply byte contains Horizontal and Vertical Lock/Unlock status, Xray activated or not, the Horizontal and Vertical polarity detection. It also contains Synchro detection status that is useful for P to assign Sync priority. A stop condition always stops all activities of the bus decoder and switches the data and the clock line (SDA and SCL) to high impedance.
2 See I C Subaddress and control tables.
I.5 - Synchro Processor The internal Sync Processor allows the TDA9106A to accept any kind of input synchro signals : - separated Horizontal & Vertical TTL-compatible sync signals, - composite Horizontal &Vertical TTL-compatible sync signals, - sync on green or composite video signal.
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TDA9106A
OPERATING DESCRIPTION (continued) I.6 - Sync Identification Status TDA9106Ais able to feed back to the MCU (thanks to I2C) the Sync input status (sync identification) so that the MCU can chooseSync priority throughI 2C. As extracted Vertical sync pulse is performedwhen choice already occured and when 12V is supplied, we recommend to use the deviceas following :(that means that even in Power management mode the IC is able to inform MCU on detected synchro signals due to its 5V supply). First, refresh Synchrodetection by I2C. Then check the status of H/V det and Vdet by I2C read. Sync priority choice should be : Table 1 : Sync Priority Choice
H/V det Yes Yes No V det Yes No No Sync priority Subaddress 03 D8 1 0 0 D7 1 1 0 Comment Synchro type Separated H & V Composite TTL H&V Sync on Green
I.8 - Synchro Inputs Both H/HVin and Vsyncin inputs are TTL compatible trigger with Hysterisis to avoid erratic detection. It includes pull up resistor to VDD. Vertical sync extractor is included for composite sync or composite video.Applicationengineer must adapt resistor R and capacitor C dedicated to its application. Figure 5
1.6V R C S/G 1 1k IREF (Typ.) = 10A
TDA9106
Of course, when choice is done, one can refresh the synchro detections and verify that extracted Vsync is present and that no synchro type change occured. Synchro processor is also giving synchro polarity information. I.7 - IC status TheIC can inform the MCUeither the 1st Horizontal PLLor Vertical sectionare locked or not, and if Xray has been activated. This last status permits to the MCU : - reset the Xray internal latch decreasing the VCC supply - directly reset throw the I2C interface.
Resistor R is fixed by detection threshold wanted : R < (VTHRESHOLD / IREF) Then C is determined by maximum pulse width to detect (in general, vertical sync width) : RC > (max pulse width) I.9 - Synchro Processor Outputs Synchro processor delivers on 3 TTL-compatible CMOS outputs the following signals : - Hout as follow :
Sync Mode Separated TTL Composite S/G Hout Mode Horizontal TTL Composite Composite Hout Polarity Same as Input Same as Input Negative
- Vsyncout is either vertical extracted pulse output or Vsyncin input. It keeps the input polarity. - Hlockoutis theHorizontal1st PLLstatus: 0Vwhen locked. It permits MCU to adjust free running frequency and optimizes the IC performance.
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9106A-31.EPS
TDA9106A
OPERATING DESCRIPTION (continued) II - HORIZONTAL PART II.1 - Internal Input Conditions Horizontal part is internally fed by synchro processor with a digital signal. corresponding to horizontal synchro pulses or to TTL composite input. Concerning the duty cycle of the input signal, the following signals (positive or negative) may be applied to the circuit. Using internal integration, both signals are recognized on condition that Z/T < 25%. Synchronization occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7s. Figure 6 designed in CMOS technology. This kind of phase detector avoids locking on false frequencies. It is followed by a "charge pump", composed of two current sources sunk and sourced (I = 1mA Typ. when locked, I = 140A when unlocked). This difference between lock/unlock permits a smooth catching of horizontal frequency by PLL1. This effectis reinforcedby an internaloriginal slow down system when PLL1 is locked avoiding Horizontal too fast frequency change. The dynamic behaviour of the PLL is fixed by an external filter which integrates the current of the charge pump. A "CRC" filter is generally used (see Figure 8). PLL1 is internally inhibited during extractedvertical sync (if any) to avoid taking in account missing pulses or wrong pulses on phase comparator.The inhibition results from the opening of a switch located between the charge pump and the filter (see Figure 9). For particular synchro type, MCU can drive Pin 3 to high level (TTL compatible input) to inhibit PLL1. It can also be used to avoid PLL1 locking on synchro inputs if a "dangerous"mode is detected by the MCU. The VCO uses an externalRC network. It delivers a linear sawtooth obtainedby chargeand discharge of the capacitor, by a current proportionnal to the currentin the resistor. Typicalthresholdsofsawtoothare 1.6Vand 6.4V. Thesetwo levels are accessibleto be filtered as on Figure 10 to improve jitter. Figure 8
PLL1F
12
An other integration is able to extract vertical pulse of composite synchroif duty cycle is more than 25% (typically d = 35%). Figure 7
9106A-33.EPS
C d d
TRAMEXT
The last feature performed is the equalizing pulses removingto avoidparasitic pulseson phasecomparator input which is intolerent to wrong or missing pulse. II.2 - PLL1 The PLL1 is composed of a phase comparator, an externalfilter and a voltagecontrolledoscillator (VCO). The phase comparator is a "phase frequency"type
9106A-32.EPS
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9106A-34.EPS
TDA9106A
OPERATING DESCRIPTION (continued) Figure 9 : PLL1 Block Diagram
H-LOCKCAP
13
PLL1INHIB PLL1F LOCK/UNLOCK STATUS
3 12
R0
11
C0
10
S/G
1
LOCKDET High SYNC PROCESSOR COMP1 E2 TRAMEXT Low CHARGE PUMP
TRAMEXT SMFE *
VSYNCIN 33 H/HVIN 38
PLL INHIBITION H-POS
14
VCO
OSC
9106A-35.EPS
* SMFE : Safety Frequency Mode Enable
PHASE ADJUST
I2C HPOS Adj.
Figure 10 : Details of VCO
I0 2
I0 9
6.4V
RS FLIP FLOP
47nF 8
47nF
Loop Filter 12 4 I0
11
1.6V
(1.3V < V12 < 6V) R0 C0
10
6.4V 1.6V 0 0.875T T
9106A-36.EPS
The control voltage of the VCO is typically comprised between 1.33V and 6V (see Figure 10). The theorical frequency range of this VCO is in the ratio 1 to 4.5, the effective frequency range has to be smaller 1 to 4.2 due to clamp intervention on filter lowest value. The synchro frequency has to be always higher than the free running frequency. As an example for a synchro range from 24kHz to 100kHz, the suggested free running frequency is 23kHz. An other feature is the capability for MCU to force horizontal frequency through I2C to 2xF0 or 3xF0 (for burn in mode or safety requirement).In this case, inhibition switch is opened leaving PLL1 free but voltage on PLL1 filter is forced to 2.66Vfor 2xF0 or 4.0V for 3xF0. The PLL1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage I2C adjustable between 2.8V and 4.0V (corresponding to 10%) (see Figure 11). This voltage has to be filtered on Pin 14 so as to optimize jitter.
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The TDA9106A also includes a Lock/Unlock identification block which senses in real time wheither PLL1 is locked on the incoming horizontal sync signal or not. The resulting information is available on Hlockout (see Synchro Processor). The block Figure 11 : PLL1 Timing Diagram
H Osc Sawtooth
7/8TH
1/8TH 6.4V 2.8VPhase REF1 H Synchro
9106A-37.EPS
Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.8V and 4.0V. The PLL1 ensures the exact coincidence between the signals phase REF and HSYNS. A T/10 phase adjustment is possible.
TDA9106A
OPERATING DESCRIPTION (continued) Figure 12 : LOCK/UNLOCK Block Diagram
5V
A From Phase Comparator NOR1
37 HLOCKOUT 20k H-Lock CAP 13 6.5V 220nF B
9106A-38.EPS
6V
function is described in Figure 12. The NOR1 gate is receiving the phase comparator output pulses (which also drive the charge pump). When PLL1 is locked, on point A there is a very small negative pulse (about 100ns) at each horizontal cycle, so after RC filter, there is a high level on Pin 13 which forces Hlockout to low level. Hysterisis comparator detects locking when Pin 13 is reaching 6.5V and unlocking when Pin 13 is decreasing to 6.0V. When PLL1 is unlocked, the 100ns negative pulse on A becomes much larger and consequently the average level on Pin 13 decreases. It forces Hlockout to go high. The Pin 13 status is approximately the following : - near 0V when there is no H-Sync - between 0 and 4V with H-Sync frequency different from VCO - between 4 to 8 V when VCO frequency reaches H-Sync one (but not already in phase) - near 8V when PLL1 is locked. Figure 13 : PLL2 Timing Diagram
H Osc Sawtooth 7/8TH 1/8TH 6.4V 4.0V 1.6V
It is important to notice that Pin 13 is not an output pin but is only used for filtering purpose (see Figure 12). The lock/unlock information is also available throw I2C read. II.3 - PLL2 Figure 14 : Flyback Input Electrical Diagram
400
HFLY 6
Q1 20k
9106A-40.EPS
GND 0V
The PLL2 ensures a constant position of the shaped flyback signal in comparion with the sawtooth of the VCO (Figure 13). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump with 0.5mA (typ.) output current. The flyback input is composed of an NPN transistor. This input must be current driven. The maximum rec omma nd ed input current is 2mA (see Figure 14). The duty cycle is fixed and equal to 48% of horizontal-period. Maximum storage time is about 43.75% - (Tfly/2.TH). Typically, Tfly/TH is around20% thatmeansTs max is around 33.75%. II.4 - Output Section The H-drive signal is transmitted to the output througha shapingblock ensuringTs and dutycycle. In order to secure scanning power part operation, the output is inhibited in the following circumstances :
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9106A-39.EPS
Flyback Internally Shaped Flyback H Drive Ts Duty Cycle 48%
TDA9106A
OPERATING DESCRIPTION (continued) Figure 16 : Output stage simplified diagram, showing the two possibilities of connection
21 VCC
20 VCC
H-DRIVE
bipolar transistor. Both the collector and the emittor are accessible (see Figure 16). Theoutput Darlington is in off-statewhen the power scanning transistor is also in off-state. The maximum output current is 20mA, and the correspondingvoltage drop of the output darlington is 1.1V typically. It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interfacehas to be designed between the circuit and the power transistor which can be of bipolar or MOS type. II.5 - X-RAY Protection The activation of the X-Ray protection is obtained by application of a high level on the X-Ray input (Pin 15 > 8V). The consequenciesof X-Ray protection are : - inhibition of H-Drive output - activation of horizontal blanking output. - activation of vertical blanking output. The reset of this protection is obtained either by VCC switch off or I2C resetby MCU (see Figure 17).
21
H-DRIVE
20
- VCC too low - Xray protection activated - During horizontal flyback - I2C bit control (voluntary inhibition by MCU). The output stage is composed of a NPN Darlington Figure 17 : Safety Functions Block Diagram
VCC Checking VCC Ref XRAY Protection XRAY VCC off or I C Reset
2
9106A-41.EPS
I2C Drive on/off HORIZONTAL OUTPUT INHIBITION I2C Ramp on/off VERTICAL OUTPUT INHIBITION I2C Blanking HORIZONTAL BLANKING OUTPUT
S R
Q
Horizontal Flyback 0.7V I2C SFME Horizontal Unlock Horizontal Free Running Detection
Vertical Flyback Vertical Sync Vertical Sawtooth Retrace Vertical Free Running Status Vertical Unlock I2C Ramp on/off
LOGIC BLOCK
VERTICAL BLANKING OUTPUT
9106A-42.EPS
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TDA9106A
OPERATING DESCRIPTION (continued) Figure 18
Horizontal Flyback Internal Trigged Horizontal Flyback Horizontal Focus Cap Sawtooth Horizontal Dynamic Focus Parabola Output 400ns
9106A-43.EPS
4.7V 2V
Moire Output
2V
II.6 - Horizontal Dynamic Focus TDA9106A delivers an horizontal parabola wave form on Pin 17. This parabola is performed from a sawtoothin phasewith flyback pulse.Thissawtooth is present on Pin 16 where the horizontal focus capacitor is the same as C0 to obtain a controlled amplitude (from 2 to 4.7V typically). Symmetry(keystone)and amplitude are I2C adjustable (see Figure 18).This signal has to be connected to the CRT focusing grids and mixed with vertical dynamic focus. Figure 19 : Moire Function Block Diagram
H-FLY Ck Q D Rst Q
II.7 - Moire Output The moire output is intented to correct a beat between horizontal video pixel period and actual CRT pixel width. The moire signal is a combinationof Horizontal and Vertical frequency signals. To achieve a moire cancellation, it has to be connected to any point on the chassis controlling the horizontalposition.We recommend to introducethis
23
Monostable
9106A-44.EPS
V-SYNC
Ck D
Q Q
Figure 20 : Moire Output Waveform
EVEN FRAME
H V MOIRE
ODD FRAME
H
9106A-45.EPS
V MOIRE
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TDA9106A
OPERATING DESCRIPTION (continued) " Horizontal Controlled Jitter" on the relative ground of PLL2 capacitor where this "controlled jitter" frequency type will directly affect the horizontal position.The amplitude of the signal is I2C adjustable. One point to notice is : (keystone adjustment). - in case H-Moire is not necessary in the applicaCorner and Corner Balance corrections may be tion, H-Moire output (Pin 2) can be turned to as a added to the E/W one. These are respectively 3rd 5 bits digital to analog converter output (0.3V to and 2nd order waveforms. 2.2V V output voltage), In order to keep a good screen geometry for any - in case of no use in application, this pin must be end user preferences adjustment we implemented left high impedance(or resistor to ground). the "geometry tracking". Due to large output stages voltage range (E/W, FOCUS), the combination of tracking function with III - VERTICAL PART maximum vertical amplitude max or min vertical III.1 - Geometric Corrections position and maximum gain on the DAC control may lead to the output stages saturation. This must The principle is represented in Figure 21. be avoided by limiting the output voltage by aproStarting from the vertical ramp, a parabola shaped priate I2C registers values. current is generated for E/W correction, dynamic For E/Wpart and Dynamic Horizontal phase control horizontal phase control correction, and vertical part, a sawtooth shaped differential current in the dynamic Focus correction. following form is generated : The base of the parabola generator is an analog I' = k' (VOUT - VDCOUT)2 multiplier the output current of which is equal to : Then I and I' are added together and converted I = k (VOUT - VDCOUT)2 into voltage for the E/W part. Where Vout is the vertical output ramp, typically comprised between 2 and 5V, Vdcout is the vertical Each of the four E/W components or the two DyDC output adjustable in the range 3.2V 3.8V in namic Horizontal phase control ones may be inhiborder to generatea dissymetric parabolaif required ited by their own I2C select bit. Figure 21 : Geometric Corrections Principle
2 VDCOUT 32 Vertical Dynamic Focus Output Vertical Ramp VOUT EW amp VDCIN
Keystone 31 Vertical Ramp VOSC EW Output
VMID VDCOUT
Corner
Corner Balance
Sidepin amp VDCOUT
To Horizontal Phase Sidepin Balance Output Current
9106A-46.EPS
Parallelogram
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TDA9106A
OPERATING DESCRIPTION (continued) The E/W parabola is available on Pin 31 by the way of an emitter follower which has to be biased by an external resistor (10k). It can be DC coupled with external circuitry. The output connection of the vertical Dynamic Focus is the same as the E/W one. This reverse parabola is available on Pin 32. Dynamic Horizontal phase control current drives internally the H-position, moving the Hfly position on the Horizontal sawtooth in the range 2.8% Th both on SidePin Balance and Parallelogram. III.2 - EW EWOUT = 2.5V + K1 (VOUT - VDCOUT) + K2 (VOUT - VDCOUT) + K3 (VOUT - VDCOUT)2 |VOSC - VMID| + K4 (VOUT - VDCOUT) |VOSC - VMID| VOSC is the ramp Pin 27 and VMID the middle of it, Figure 22 : Vertical Part Block Diagram
CHARGE CURRENT TRANSCONDUC TANCE AMPLIFIER
typically 3.5V K1 is adjustable by EW amplitude I2C register K2 is adjustable by Keystone I2C register K3 is adjustable by Cbow Corner I2C register K4 is adjustable by Spin Corner I2C register III.3 - Dynamic Horizontal Phase Control IOUT = K5 (VOUT - VDCOUT )2 + K6 (VOUT - VDCOUT) K5 is adjustable by SidePin Balance I2C register K6 is adjustable by Parallelogram I2C register III.4 - Vertical Dynamic Focus VFOCOUT = 6V - 0.7 (VOUT - VDCOUT)2 No adjustment is available for this part except by means of tracking. III.5 - Vertical Sawtooth Generator
2
REF 27 S/G 1 VSYNCIN 33 H/HVIN 38 SYNC PROCESSOR DISCH. OSCILLATOR OSC CAP SAMPLING 25 SAMP. CAP S CORRECTION VS_AMP SUB07/6bits POLARITY COR_C SUB08/6bits C CORRECTION Vlow
Sawth. Disch.
29 VERT_OUT VERT_AMP SUB05/7bits
Corner SUB0B/6bits
Corner Balance SUB0C/6bits
CORNER
PARABOLA GENERATOR
31 EW_OUT
EW_CENT EW_AMP SUB0A/6bitsSUB09/6bits
SPB_OUT
Internal Signal to PLL2 PARAL SUB0E/6bits SPB_AMP SUB0D/6bits
32 V_FOCUS
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9106A-47.EPS
TDA9106A
OPERATING DESCRIPTION (continued) The vertical part generates a fixed amplitude ramp which can be affectedby S and C correction shape. Then, the amplitude of this ramp is adjustedto drive an external power stage (see Figure 22). The internal reference voltage used for the vertical part is available between Pin 26 and Pin 24. Its typical value is : V26 = VREF = 8V The charge of the external capacitor on Pin 27 (VCAP) generates a fixed amplitude ramp between the internal voltages, Vl (Vl = VREF/4) and VH (VH = 5/8 x VREF). When the synchronization pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 106Hz. Typical free running frequency can be calculated by : COSC A negative or positive TTL level pulse applied on Pin 33 (VSYNC) as well as a TTL composite sync on Pin 38 or a Sync on Green signal on Pin 1 can synchronise the ramp in the range [fmin , fmax]. This frequency range depends on the external capacitor connected on Pin 27. A capacitor in the range [150nF, 220nF] 5% is recommanded for application in the following range : 50Hz to 120Hz. Typical maximum and minimum frequency, at 25oC and without any correction (S correction or C correction), can be calculated by : f(Max.) = 2.5 x f0 and f(Min.) = 0.33 x f0 If S or C corrections are applied, these values are slighty affected. If a synchronization pulse is applied, the internal oscillator is automaticaly synchronized but the amplitude is no more constant. An internal correction is activated to adjust it in less than a half a second : the highest point of the ramp (Pin 27) is sampled on the sampling capacitor connected on Pin 25 at each clock pulse and a transconductanceamplifier generates the charge current of the capacitor. The ramp amplitude becomes again constant and frequency independant. The read status register enables to have the vertical Lock-Unlock and the vertical Sync Polarity inf0 (Hz) = 1.6 e-5 formations. It is recommanded to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory. Good stability of the internal closed loop is reached by a 470nF 5% capacitorvalue on Pin25 (VAGC). Pin 30, VFLY is the vertical flyback input used to generate the vertical blanking signal on Pin 23. If Vfly is not used, (VREF - 0.5), at minimum, must be connected to this input. In such case, the vertical blanking output will be activated by the vertical sync input signal and resetted by the end of vertical sawtooth discharging pulse. III.6 - I2C Control Adjustments Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are generated internally. Their amplitude are adjustable by their respective I2C register. They can also be inhibited by their Select bit. At the end, the amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude control register. The adjusted ramp is available on Pin 29 (VOUT) to drive an external power stage. The gain of this stage is typically 25% depending on its register value. The DC value of this ramp is kept constant in the frequency range, for any correction applied on it. its typical value is VMID = 7/16 VREF. A DC voltage is available on Pin 28 (VDCOUT). It is driven by its own I2C register (vertical Position). Its value is VDCOUT = 7/16 VREF 300mV. So the VDCOUT voltage is correlated with DC value of VOUT. It increases the accuracy when temperature varies. III.7 - Basic Equations In first approximation,the amplitude of the ramp on Pin 29 (Vout) is : VOUT - VMID = (VOSC - VMID) (1 + 0.25 (VAMP)) with VMID = 7/16 VREF ; typically 3.5V, the middle value of the ramp on Pin 27 VOSC = V27 , ramp with fixed amplitude VAMP is -1 for minimum vertical amplitude register
1
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TDA9106A
APPLICATION DIAGRAMS Figure 23 : Demonstration Board
+12V
PC2 47k ICC1 - MC14528 CC4 1 TA1 47pF +12V 2 TA2 3 CDA 4 IA 5 IA 6 QA 7 QA 8 GND V CC 16 TB1 15 TB2 14 CDB 13 IB 12 47pF CC3
CC2 10F
CC1 100nF
J16
1
J15 +5V
1 +5V
J14
4 3 2 1 C39 22pF C40 C45 10F R49 22k
IC3 - STV9422 R43 24 PWM7 23 PWM6 22 TEST 21 B +5V 20 G 19 R 18 GND 17 RST PWM0 1 PWM1 2 FBLK 3 VSYNC 4 HSYNC 5 V DD 6 PXCK 7 CKOUT 8 XTALOUT 9 XTALIN 10 PWM2 11 PWM3 12 33pF X1 8MHz 33pF C7 47F C7 L2 10H +5V C43 10k
C42 1F J13 1 TILT
PC1 47k +12V C44 10pF J10 R22 1.5k R48 1k C26 1 1F R44 2 10k TP9 MOIRE SYNC/G
R39 4.7k
R29 4.7k
R42 100 R41 100
+12V
IC2 TDA9106
GNDD 42
22pF
IB 11 QB 10 QB 9
SDA 41
16 SDA 15 SCL 14 PWM5
3 JP1 R20 10 HREF R35 10k R10 10k C25 33pF C33 100nF C27 47F 6 C16 220pF 7 J8 1 HFLY C21 47nF C22 33pF R8 10k TP15 C23 47nF 9 8 5 C7 4 22nF
PLLINH
SCL 40
13 PWM4 L1 10H
PLL2C
+5V 39 TP1
+5V C30 100F J11 C32 100nF
HREF
H/HVIN 38 TP17
HSYNC
HFLY
HLOCKOUT 37
TP10 R30 10k R31
HGND
HOUT 36
TP11 +12V C36 1F R37 27k 27k R15 1k
FC2
VSYNCOUT 35
TP12
R17 270k R19 270k C11 220pF R38 2.2 1W
J1 1 E/W
FC1
TEST 34 J12
Q1 Q2 BC557 R34 1k VSYNC
C28 10 C0 820pF 5% R23 11 R0 6.49k 1% C13 10nF 12 PLL1F EWOUT 31 V_FOCUS 32 VSYNCIN 33 TP16
TP17
R33 4.7k
R9 470
R18 39k
Q3 TIP122
V_FOCUS R28 10k
E/W POWER STAGE
J2 D2 1N4148 D1 1N4004 R32 1 C14 470F +12V C9 100nF -12V TP8 C18 100F 36V TP7 15k
C31 R36 1.8k 4.7F 13 HLOCKCAP C17 220nF VFLY 30 4.7k R16
1 J3
C29 R45 TP14 XRAYIN J7 1 33k DYNAMIC FOCUS J9 1 1k R24 10k +12V C5 100F R25 33k R7 10k
1F
14 HPOS
VOUT 29
R40 12k VREF R2 5.6k R1 C12 12k C41 470pF R5 5.6k C4 7 100nF TP5 1 2 6 IC1 TDA8172 4 3 5 R3 1.5 C1 220nF C8 100nF R11 220 1/2W R4 1 1/2W
15 XRAYIN
VDCOUT 28
J18 1 2 3 V YOKE
R45 V_FOCUS
C34
820pF
16 H_FOCUSC
VCAP 27 150nF
17 H_FOCUS
VREF 26 C2 100nF
VREF C3 47F
VERTICAL DEFLECTION STAGE
C10 -12V 470F
R47 L3 10H +12V C20 1F R13 1k C35 100nF C19 100F 63V STD Q6 5N20 R12 560 R14 22k C24 1nF T1 82 3W G5676-00
C15 C6 100nF 18 VCC VAGCCAP 25 470nF
+24V J17 1 2 3
19 GND
VGND 24
Q5 BC547 R6 10 Q4 BC557
HDRIVE
20 HOUTEM + 12V R21 3.9k TP2 TP8 HBLK VBLK R27 3.9k
V_BLKOUT 23
HORIZONTAL DRIVER STAGE
21 HOUTCOL
H_BLKOUT 22
TP3 TP4 1 J6
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9106A-48.EPS
TDA9106A
APPLICATION DIAGRAMS (continued) Figure 24 : PCB Layout
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9106A-49.EPS
TDA9106A
APPLICATION DIAGRAMS (continued) Figure 25 : Components Layout
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9106A-50.EPS
TDA9106A
PACKAGE MECHANICAL DATA 42 PINS - PLASTIC SHRINK DIP
E E1
A1
A2
B
B1
e
L
A
e1 e2
D c E 42 22
.015 0,38 Gage Plane
1
21
SDIP42
e3 e2
Dimensions A A1 A2 B B1 c D E E1 e e1 e2 e3 L
Min. 0.51 3.05 0.38 0.89 0.23 36.58 15.24 12.70
Millimeters Typ.
Max. 5.08 4.57 0.56 1.14 0.38 37.08 16.00 14.48
Min. 0.020 0.120 0.0149 0.035 0.0090 1.440 0.60 0.50
Inches Typ.
Max. 0.200 0.180 0.0220 0.045 0.0150 1.460 0.629 0.570
3.81 0.46 1.02 0.25 36.83 13.72 1.778 15.24
0.150 0.0181 0.040 0.0098 1.450 0.540 0.070 0.60
2.54
3.30
0.10
0.130
Information furni shed is believed to be accurate and reliable. However, SGS-THOMSON Micr oelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise und erany patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This pu blication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1997 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I 2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
30/30
SDIP42.TBL
18.54 1.52 3.56
0.730 0.060 0.140
PMSDIP42.EPS

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